1. Field of the Invention
The present invention generally relates to a plasma-enhanced processing of semiconductor wafers and, more specifically, to an apparatus for improving voltage stability on a workpiece and electrical coupling between a plasma and the workpiece in a semiconductor wafer processing system.
2. Description of the Related Art
Plasma-enhanced reactions and processes have become increasingly important to the semiconductor industry, providing for precisely controlled thin-film depositions. For example, a plasma reactor in a high-temperature physical vapor deposition (PVD) semiconductor wafer processing system generally comprises a reaction chamber for containing a working gas, a pair of spaced-apart electrodes (cathode and anode) that are driven by a high power DC voltage to generate an electric field within the chamber, and a substrate support or pedestal for supporting a substrate within the chamber. The cathode is typically a target material that is to be sputtered or deposited onto the substrate, while the anode is typically a grounded chamber component. The electric field creates a reaction zone where electrons are captured near the cathode surface. This condition increases the number of ionizing collisions the electrons have with working gas neutral atoms, thereby ionizing the working gas into a plasma. The plasma, characterized by a visible glow, forms as a mixture of positive ions, neutrals and negative electrons. Ions from the plasma bombard the negatively biased target releasing deposition material. As such, a deposited film forms on the substrate which is supported and retained upon the surface of the pedestal. Additionally, hardware is used to prevent deposition from occurring in unwanted locations. For example, a waste ring and a cover ring prevent deposition material from being deposited on surfaces other than the substrate and process shields.
To further enhance deposition in an ion metallization system, a specific type of PVD system, the substrate and pedestal are biased negatively with respect to the plasma. This is accomplished by providing RF power to the pedestal. A negative DC offset accumulates on the pedestal as a result of the higher mobility of electrons as compared to the positive ions in the plasma. In some processes, as neutral target material is sputtered from the target and enters the plasma, the target material becomes positively ionized. With the negative DC offset at the pedestal, the positively ionized target material is attracted to and deposits on the substrate in a highly perpendicular manner. That is, the horizontal component of acceleration and/or velocity of the positive ion is reduced while the vertical component is enhanced. As such, the deposition characteristic known as xe2x80x9cstep coveragexe2x80x9d is improved. Ordinarily, a 400 KHz AC source is used to bias the pedestal, but other frequency sources such as a 13.56 MHz source may also be used.
Ideally, the voltage magnitude at the substrate (i.e., a semiconductor wafer) remains stable during processing and is reproducible from wafer-to-wafer over an entire processing cycle. That is, the voltage level at the wafer remains constant as the target material is being deposited onto the wafer. A stable voltage level at the wafer causes the ionized deposition material to be drawn uniformly to the wafer. A uniform deposition film layer is a highly desirable characteristic in the semiconductor wafer manufacturing industry. Additionally, the same stable voltage magnitude must reproduce or occur as each new wafer is processed. Reproducing the same stable voltage magnitude for each new wafer is also desirable as it reduces the amount of improperly processed wafers and improves the accuracy of the film deposition amongst a batch of wafers. As such, overall quality of manufactured product increases.
The characteristics of voltage stability and reproducibility are optimized when the wafer is the only electrical conductor in direct contact with the plasma. That is, voltage stability and reproducibility are maintained when the wafer forms the path of least resistance for the RF power to couple through. Existing pedestal configurations allow for various electrical paths wherein voltage stability is compromised. Specifically, stability is compromised due to the hysteresis effect of power coupling through multiple paths to the plasma. One such electrical path establishes through one of the aforementioned rings in the process chamber. The rings (which are in electrical contact to the pedestal) are made of conductive material (e.g., stainless steel) which have instantaneous impedance values that are lower than the impedance of the pedestal/wafer combination. As such, the RF power couples to the plasma through one or more of the rings in lieu of, or in addition to, a path through the wafer. When a ring becomes the momentary path of least resistance, energy losses in the system and voltage instability at the wafer occurs. The resultant instability of the wafer voltage causes the aforementioned nonuniformity of film deposition on the wafer. For example, coverage of the bottom of particular feature (i.e., trench) on the wafer is not as thick as the sidewalls. Process repeatability (the ability to duplicate identical process conditions for a large number of individually processed wafers) also suffers as a result of the aforementioned undesirable conditions.
Consequently, there is a need to electrically enhance and thereby define a primary conductive path from the pedestal to the plasma, via the wafer. Defining such a path stabilizes wafer voltage thereby improving the deposition process. Therefore, there is a need in the art for an apparatus that optimally conducts power from a pedestal through the wafer and plasma to optimize wafer voltage stability and process condition reproducibility.
The disadvantages heretofore associated with the prior art are overcome by an apparatus for optimally coupling power through a wafer in a semiconductor wafer processing system. The inventive apparatus has a pedestal assembly and a pedestal cover positioned over a top surface of and circumscribing the pedestal assembly for electrically isolating the pedestal assembly. The pedestal assembly further comprises a lower shield member, an insulating plate member disposed upon the lower shield member with the pedestal disposed upon the insulating plate member and an insulative isolator ring disposed upon an outer flange portion of the lower shield member such that a lower, horizontal portion of said isolator ring is below and spaced apart from the pedestal. A plurality of rest buttons provided in a plurality of hollow portions in the pedestal assembly and passing through a plurality of openings in the pedestal cover support the wafer above the pedestal cover.
In sum, the pedestal cover defines a conductive pathway for coupling RF wafer biasing power during wafer processing. By selecting the appropriate frequencies and pedestal cover materials, RF wafer biasing power couples only through the wafer and not through neighboring pedestal components which may exhibit instantaneous conductive characteristics. As such, voltage stability at the wafer and process condition reproducibility is maintained which improves ion deposition from the plasma.